ESD Low Voltage Driver Block Diagram

Document #:

LIGO-D1400301-v11

Document type:

D - Drawings

Abstract:

A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.

Files in Document:

• PDF Version (NewESD_v11.pdf, 89.4 kB)

Other Files:

• Visio Version (NewESD_v11.vsd, 305.5 kB)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Sensing and Control

Authors:

• Rich Abbott
• Peter Fritschel
• Carl Adams

Keywords:

ESD

Notes and Changes:

Version 11 Notes:
Updated TVS to a diode clamp. Added DAC noise model equation. Updated 200 ohm series current limiting resistor. Added Test Port and binary readbacks.

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