LIGO Document D2000329-v2

PCIe Timing Interface Board

Document #:
Document type:
D - Drawings
Other Versions:
Schematics and PCB of the PCIe timing interface.

Notes and Changes:
Minor changes to the PCB, added RS485 transciever, more clock options, and test points.
First Run - L1 changed to 33nH, C23 removed, R5 reduced to 5k.
R94 is changed to adjust range of the VCXO. 22k for Bomar, 7.15k for Vectron.
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