LIGO Document E2000625-v2

ECR: Upgrade existing DAQ front-end chassis with new PCIe timing boards

Document #:
LIGO-E2000625-v2
Document type:
E - Engineering documents
Other Versions:
Abstract:
As part of A+ we developed a new timing interface that directly plugs into an PCI Express slot. This solution is fully compatible with the existing LIGO timing distribution system. It has the ability to support multiple sampling rates within the same chassis and is required to support the new 524kHz sampling ADCs for the filter cavity design.
Files in Document:
Other Files:
Keywords:
ECR
Notes and Changes:
associated FRS ticket:
https://services.ligo-la.caltech.edu/FRS/show_bug.cgi?id=16594
V2 has Updated amounts, cost estimates, source of funding

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