LIGO Document T1100367-v2
- A short test procedure to verify an AA chassis is wired correctly and the boards are functional from a high level perspective. This procedure is for functional testing at the chassis level only assuming all the PCBs inside the chassis have been thoroughly tested per the regular procedure.
- PDF Version (Adl_AA_AI_chassis_level_TestPlan-v2.pdf, 19.1 kB)
- Other Files:
- Word Version (Adl_AA_AI_chassis_level_TestPlan-v2.docx, 45.9 kB)
- Updated a few typos, and Ben added the capability of using this procedure for AI chassis checkout
DCC Version 3.4.2, contact