LIGO Document T1900639-v1

PCIe Implementation of Timing Interface System

Document #:
Document type:
T - Technical notes
Other Versions:
PCIe Implementation of Timing Interface System.
timing slave pcie
Notes and Changes: (adnaco backplane)

Moving to the ARTIX 7 Xilinx Chips for better PCIe integration.

I am considering what system configurations this board is implemented in, and I want to be certain that it can continue to work in these applications.

* Timing Slave - Basis for all of this, I have fit this the PCIE board layout so far.

* Duotone Board & Adapter - This is straight forward and should be simple enough to implement on the timing board.

* 1PPS Locking - Again should be simple enough.


* RF Source

* Timing Slave

* Timing Master

* Backplane

* New Backplane LVDS

* ADL General Standards DAC

* ADL General Standards ADC

* Contec Cards

Referenced by:

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