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Design Rule Verification Report

Date : 6/14/2009
Time : 4:52:16 PM
Elapsed Time : 00:00:02
Filename : C:\Users\daniel\Protel\RF\VCO\VCOSource.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=7.8mil) ((HasFootprint('SC70')) or (HasFootPrint('SSO-G8/NARROW')) or (HasFootPrint('SO-G5/E2.4'))),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=15mil) (Max=200mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silkscreen Over Component Pads (Clearance=1mil) (All),(All) 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Total 0