Altium

Design Rule Verification Report

Date:		7/28/2016
Time:		12:06:41 PM
Elapsed Time:		00:00:03
Filename:		D:\Users\daniel\Protel\CommonMode\Options\Lowpass\Lowpass.pcbdoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Routing Via (MinHoleWidth=15mil) (MaxHoleWidth=28mil) (PreferredHoleWidth=15mil) (MinWidth=35mil) (MaxWidth=50mil) (PreferedWidth=35mil) (All)	0
Routing Layers(All)	0
Clearance Constraint (Gap=10mil) (All),(All)	0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=15mil) (All)	0
Net Antennae (Tolerance=0mil) (All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=10mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All)	0
Hole Size Constraint (Min=15mil) (Max=250mil) (All)	0
Pads and Vias to follow the Drill pairs settings	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Total	0