Altium

Design Rule Verification Report

Date: 9/16/2019
Time: 11:42:07 AM
Elapsed Time: 00:00:01
Filename: C:\Users\daniel.sigg\Documents\Protel\RF\VCO\VCOBox.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (InNetClass('Diff_Imp')),(All) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Clearance Constraint (Gap=7.8mil) ((HasFootprint('SC70')) or (HasFootPrint('SSO-G8/NARROW')) or (HasFootPrint('CP_32_2')) or (HasFootPrint('HCP_16_1')) or (HasFootPrint('HCP_24_1')) or (HasFootPrint('JR1608-0603'))),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=15mil) (All) 0
Width Constraint (Min=50.00ohms) (Max=50.00ohms) (Preferred=50.00ohms) (InNetClass('Controlled_Imp')) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Minimum Annular Ring (Minimum=4mil) (IsVia) 0
Minimum Annular Ring (Minimum=8mil) (HasFootprint('278LF')) 0
Hole Size Constraint (Min=8mil) (Max=100mil) (IsVia) 0
Hole Size Constraint (Min=15mil) (Max=200mil) (IsPad) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=2mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Silk to Silk (Clearance=6mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0