LIGO Document T2400089-v1

IIR Filter Bank for FPGAs

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T - Technical notes
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An IIR filter can be implemented as a series of second order sections (SOS). Here we look at an FPGA implementation written in VHDL code in Vivado and targeting the Xilinx 7-series and Ultrascale devices. The filter implementation uses a fixed-point number representation with 52-bits that is roughly equivalent to a double precision number.
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